Copper layer 435 can be a layer of copper positioned in proximate location to via section 420. Copper layer 435 can be an alloy including copper (Cu). In an alternative embodiment, copper layer 435 is a stack of several layers.
Semiconductor devices or integrated circuits (ICs) can include millions of devices, such as, transistors. Ultra-large scale integrated (ULSI) circuits can include complementary metal oxide semiconductor (CMOS) field effect transistors (FET). Despite the ability of conventional systems and processes to fabricate millions of IC devices on an IC, there is still a need to decrease the size of IC device features, and, thus, increase the number of devices on an IC. Nevertheless, there are many factors that make the continued miniaturization of ICs difficult. For example, as the size of vias (or pathways between integrated circuit layers used to electrically connect separate conductive layers) decreases, electrical resistance increases.
One way by which integrated circuit (IC) manufacturers have attempted to reduce via resistance as the via size decreases is reducing the thickness of the barrier material. For example, IC manufacturers can try to make the barrier material very thin at the bottom of the via. The thickness of the barrier material can be reduced by chemical vapor deposition (CVD) or advanced plasma vapor deposition (PVD) processes. Nevertheless, reducing the barrier thickness causes the barrier to become more permeable to copper (Cu) diffusion, which can adversely affect resistance to electromigration (EM).
FIG. 1 illustrates a schematic cross-sectional view of a portion 100 of an integrated circuit including a copper layer 110, a via 120, and a copper layer 130. Via 120 and copper layer 130 are separated by a barrier layer 140. Copper layer 110 and via 120 can be one structure when formed in a dual in-laid process or, alternatively, two structures when formed in a single in-laid process. Barrier layer 140 inhibits diffusion of copper ions in general. Conventional barrier layers can include Tantalum Nitride (TaN).
Portion 100 also includes a dielectric layer 142 that is separated from copper layer 130 by an etch stop layer 144. Dielectric layer 142 can be oxide and etch stop layer 144 can be Silicon Nitride (SiN). Etch stop layer 144 prevents diffusion of copper from copper layer 130 into dielectric layer 142.
As discussed above, conventional systems have attempted to reduce the thickness of barrier layer 140 to reduce the resistance associated with via 120. However, this reduction in thickness can cause electromigration (EM) failures. FIG. 2 illustrates portion 100 described with reference to FIG. 1, further having an EM failure 145 in copper layer 130. FIG. 3 illustrates portion 100 having an EM failure 155 in via 120 due to bulk diffusion from copper layer 110.
EM failures have been described by Stanley Wolf, Ph.D. in Silicon Processing for the VLSI Era, Vol. 2, pp. 264-65. Dr. Wolf explains that a positive divergence of the motion of the ions of a conductor leads to an accumulation of vacancies, forming a void in the metal. Such voids may ultimately grow to a size that results in open-circuit failure of the conductor line.
Thus, there is a need for a barrier that is more resistant to copper diffusion and thin enough for low via resistance. Further, there is a need for a method of implanting copper barrier material and bulk barrier material to improve electrical performance. Even further, there is a need for a method of enhancing barrier properties by inserting alloy elements to reduce copper diffusion and bulk diffusion.
An exemplary embodiment is related to a method of fabricating an integrated circuit. This method can include forming a barrier material layer along lateral side walls and a bottom of a via aperture which is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer, implanting a first alloy element into the barrier material layer, and implanting a second alloy element after deposition of the via material. The implanted first alloy element can make the barrier material layer more resistant to copper diffusion. The implanted second alloy element diffuses to a top interface of the via material and reduces interface diffusion from the via material.
Another exemplary embodiment is related to a method of implanting copper barrier material to improve electrical performance in an integrated circuit fabrication process. This method can include providing a copper layer over an integrated circuit substrate, providing a barrier material at a bottom and sides of a via aperture positioned over the copper layer to form a barrier material layer separating the via aperture from the copper layer, amorphizing the barrier material layer thereby making the barrier material layer more resistant to copper diffusion from the copper layer, and filling the via aperture with a via material and an alloy element that diffuses to a top interface of the via material.
Another exemplary embodiment is related to a method of forming a via in an integrated circuit. This method can include depositing a copper layer, depositing an etch stop layer over the copper layer, depositing an insulating layer over the etch stop layer, forming an aperture in the insulating layer and the etch stop layer, providing a barrier material at a bottom and sides of the aperture form a barrier material layer providing separation from the copper layer, implanting a first alloy element into the barrier material layer, filling the aperture with a via material and a second alloy element to form a via, and providing a conductive layer over the via such that the via electrically connects the conductive layer to the copper layer. The implanted first alloy element can make the barrier material layer more resistant to copper diffusion from the copper layer. The second allow element can diffuse to a top interface to reduce copper diffusion.